Digital logic progress (by alaric)
But to make rapid prototyping of CPU designs faster, without losing the direct contact with hardware concerns that would be had by going to VHDL, I also plan to add a PAL device. It'd have the delay of a NOT/AND/OR network, like a sum-of-products PAL, but would implement any given boolean logical expression for each output pin by direct evaluation.
The simulation of a PAL would be a slight approximation; it wouldn't actually convert your expression to sum of products form and deduce the PAL layout. So it wouldn't be able to work out power consumption or area accurately, since it wouldn't know how many gates would actually be in the PAL. But it'd be an easier way of specifying complex logical functions than setting up a network of gates, and when the prototype design becomes more like a 'final' design, I can then either hand-code the gate network or actually write a logical minimizer that converts the expressions into a network automatically.
On the same principle, I can also produce a state machine device that simulates the usual Moore/Mealey machine; given a number of inputs pins, a clock input, a reset input, a number of output pins, and a descriptive list of named states, each with what outputs to generate in that state and which state to go to on the next clock tick as a function of the inputs, we can simulate the behaviour of a typical implementation of that state machine in terms of a set of D flip-flops with next-state and output logic. Again, it will be an approximation, since the system won't actually assign bit patterns to states and work out the logic, but will instead use ballpark figures for propagation delays based on the technology's timings for logic and flip-flops.
Those two devices will make experimenting with instruction decode logic and execution units, respectively, much easier.
Electronics | alaric | 
Fri 30th Jun 2006 1:11 am
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By andyjpb, Sat 1st Jul 2006 @ 2:04 pm
Can you implement a PAL using a ROM?