Digital logic progress (by alaric)
Also, I've implemented technology files to contain timing (and, later, power consumption) details of devices. Eg, one would be able to simulate the same circuit using a chosen logic technology and see what the result was; I have databooks that give timings for 74 series discrete logic, (including original 74, 74S, 74LS, 74ALS, 74HC, 74HCT, 74F, and 74ACT), and I have some references that give the logic timings for ASIC gates in current CMOS processes (90nm and up), and I plan to obtain timings for circuit implementations in various FPGAs on the market.
Yes, power consumption is on the cards. I want to obtain standby and switching current figures for gates, so the simulator can track the power consumed in each unit of time simulated. The power consumption rate, and total energy consumption so far, can then be output as analogue variables in the VCD output file. With a bit of Fourier analysis, this can even be used to guesstimate the frequency distribution of electromagnetic noise produced by the circuit, although a 'real' figure for that would depend on the layout of signal traces.
I may also add parameters in the technology file to work out approximate circuit area; for the 74xx series logic this would be in square centimetres based on the size of a DIL IC plus PCB area, but for the CMOS processes it'd be in square millimetres of silicon.
Size and power consumption are important factors of a circuit design.
But the main challenge ahead is to implement as many devices as possible. Right now, I have the standard combinational logic toolset; AND/NAND/OR/NOR/XOR/XNOR/NOT, plus a series of line drivers (tristate, open drain, open source, weak logic output, and plain noninverting buffer). I need to add transmission gates, latches and flip-flops (both with pedantic enforcement of setup and hold times, complete with metastable states), and a better memory device with pedantic timings and optional wait-state handshaking (to emulate more complex memory systems with variable access time like DRAMs behind a cache, etc).
Electronics | alaric | 
Fri 30th Jun 2006 1:11 am
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By andyjpb, Sat 1st Jul 2006 @ 2:04 pm
Can you implement a PAL using a ROM?